Integrated circuits have to be able to send and to receive electrical signals to and from external or “off-chip” elements. This communication with off-chip elements is typically achieved through the use of buffer circuits, also commonly referred to simply as “buffers.” FIGS. 1 and 2 show the layouts of conventional integrated circuits, illustrating the placement of buffer circuits therein.
With reference initially to FIG. 1, an integrated circuit die 100 includes a plurality of buffer circuits 102 arranged adjacent to its periphery as shown. Associated with each of the buffer circuits 102 is a corresponding bonding pad 104, which may be viewed as an example of what is more generally referred to herein as a signal pad.
FIG. 2 shows an integrated circuit die 100′ which includes peripherally-arranged buffer circuits 102 as in FIG. 1 but also includes an area array 106 comprising additional buffer circuits. Again, associated with each of the buffer circuits 102 is a corresponding bonding pad 104. This placement allows many more buffer circuits to be placed on a single integrated circuit die than the simple outer perimeter placement of FIG. 1. During manufacturing of a packaged integrated circuit with area array buffers, a special technique called solder bumping is often used to allow all of the bonding pads in the area array to be connected to corresponding signal paths in the structure in which the integrated circuit die is packaged.
A problem associated with use of area array buffers such as those shown in FIG. 2 is that it is difficult to gain access to internal analog signal pads during testing that occurs before the integrated circuit die is packaged. Such pre-package testing typically involves testing the integrated circuit die while it is still part of the semiconductor wafer, that is, before the wafer is cut into chips which are individually packaged, and is thus also referred to herein as wafer-level testing. The wafer-level testing is carried out using a wire-type wafer probe card comprising many short but stiff wires, referred to as test probes, that temporarily connect the peripheral bonding pads of the integrated circuit die to an associated test apparatus.
FIG. 3 illustrates the application of a set of wafer test probes 108 to a set of bonding pads associated with peripheral buffers 110 on one side of the integrated circuit die 100′. For clarity and simplicity of illustration, this figure shows only the left side of the integrated circuit die being probed, but in practice all four sides are probed at the same time using the same wire-type wafer probe card. Unfortunately, a standard wire-type wafer probe card can only contact the peripheral bonding pads, and cannot reach the bonding pads which are inside the area array.
Although there is another type of wafer probe card, known as a membrane probe card, which can reach internal bonding pads within an area array during wafer-level testing, this type of card is generally very expensive and difficult to use.
One possible alternative is to provide permanent connections between the bonding pads inside the area array to corresponding peripheral bonding pads for wafer-level testing. However, this approach is usually appropriate only for digital signal pads, since for analog signal pads the connecting wires may add unacceptable amounts of parasitic resistance and capacitance, thereby degrading analog signal performance during normal operation of the subsequently-packaged integrated circuit.
It is therefore apparent that a need exists for improved techniques for providing wafer-level test access to internal analog signal pads of an integrated circuit die, without the excessive cost and other difficulties associated with use of a membrane probe card.